DMA
A data channel moves a word from a tape into core storage without the processor executing a single instruction to do it. IBM's manual says so plainly, and every account of direct memory access since has said the same: the processor is free to compute. None of them says how much less computing it gets done. The same manual answers that on the next page but one, in a list of what the channel is for, and the answer is one storage cycle for each word processed. There is one core store and the channel reaches it through the same multiplexor the processor does, so the transfer is not free. It is stolen, a cycle at a time, and everything on this page is that one division against the two basic cycles the manual prints.
New to how a device gets data into memory? Start here
A processor moves data by executing instructions: load this word, store it there, count, repeat. A device that wants to put a tape reel into memory can be handled that way, and every word of it then costs the processor a handful of instructions it could have spent on the actual work. A data channel is a second, much simpler machine that does the moving instead. The processor tells it which device and which area of memory, and then goes back to computing.
That is where most explanations stop, and it is where the interesting part starts. There is only one core store, and the channel reaches it through the same switching the processor does. So the processor is not executing the transfer and is still paying for it, one memory cycle per word, and this page is that one division.
Fast and forgetful, or slow and permanent
Memory is quick and loses everything when the power goes. A disk keeps what it was given and is slower by a factor with several zeroes in it. Parts that are both do exist and none has been cheap or plentiful: battery-backed memory modules are still made, and the fastest persistent part on the market was discontinued.
So nearly every design in this topic is buying one with the other. Keep it in the fast part and you are quick until the lights go out. Write it to the slow part first and you are safe but waiting. The machines here are the arrangements people found in between, and each of them is honest about which half it gave up.
The machine for this idea on its own is Write-Ahead Log, if you would rather press it than read about it.
The processor did not copy these bytes, and it paid for them anyway
1 One word off a tape into core storage, and the single storage cycle the manual charges for it
IBM's own manual states the freedom on page 4: the data channel carries data between the input-output units and core storage in a transmission that is independent of computing
, and The stored program may then proceed to execute instructions (compute), not related to the input transmission.
Every account of direct memory access stops at that sentence. Page 6 is where the manual prices it, in the list of what the channel is for: one storage cycle of 2.4 usec is used for each word processed. Independent is true. Free is a different word.
| quantity | value | where it comes from |
|---|
2 That cycle against the cycles the core can serve, which is a straight line to a rate at which nothing else runs
The share is a straight line in the device rate, so there is a rate at which one channel consumes the entire core and the processor stops. No account of this mentions such a number, because none of them price a word. The machine works it out from the cycle time alone, and then puts the manual's fastest tape beside it.
| characters a second | words a second | core taken | left to compute |
|---|
3 Every channel the machine allows at once, on the two basic cycles the manual prints
The manual gives both limits in one sentence apiece: The 7090 uses a maximum of eight input-output data channels. The 709 has no more than six.
Channels are additive here, because each word is one cycle whichever channel assembled it. Run every channel the machine allows at the fastest tape it lists, and the two answers are not close to each other.
| machine | basic cycle | core taken | left to compute | within its own channel limit |
|---|
These ran in this browser when the page loaded. Each claim, whether it held, and the number behind it.
| claim | held | measured |
|---|---|---|
| a character is six bits, and the manual never says so | yes | 375,000 binary digits a second at 62,500 characters a second gives 6, and 90,000 at 15,000 gives the same |
| so a 36-bit word is six characters, and a channel word is one storage cycle | yes | 36 bits a word over 6 bits a character is 6 |
| an addition is two storage cycles on both machines | yes | 24 over 12 and 4.8 over 2.4, both exactly two |
| and the manual's printed 41,660 and 208,330 are its own rounding, which it says | yes | the divisions give 41666.67 and 208333.33; the chart prints 41,660 and 208,330 under the line "Operations-per-second numbers are approximate" |
| one 729 IV takes 2.5 per cent of a 7090's core, so independent of computing is true and free is not | yes | 10416.67 words a second against 416666.67 storage cycles a second |
| the same drive costs 5 times as much on a 12 usec machine, and the cycle is the only thing that changed | yes | 12.5 per cent against 2.5, a ratio of exactly 5 |
| eight channels of 729 IV take 20 per cent of a 7090; six take 75 per cent of a 709 | yes | the manual gives both limits: eight channels on the 7090, no more than six on the 709 |
| a single channel would consume the whole core at 2,500,000 characters a second | yes | no tape in Chart 2 comes near it; the fastest listed is 62,500, which is 2.5 per cent of the way there |
What is real here, and what is not
The two constants the manual never states are divisions of two it does
A character is six bits and a word is six characters, and neither sentence appears in the document. Both are forced by figures that do: the tape panel gives 375,000 binary digits a second beside 62,500 characters a second, and 90,000 beside 15,000, and both divisions give six. Page 4 gives the word as 36 bits in parallel. So six characters a word is derived here rather than brought in from outside, and the page checks it when it opens rather than asserting it.
One cycle a word is the 7090 data channel's stated behaviour, and the 12 usec column is the reader's arithmetic
Page 6 says one storage cycle of 2.4 usec is used for each word processed, and that sentence is about the 7090's channel. The 12 usec figure is the 709's and the 704's basic cycle from the same comparison table, and this page applies the one-cycle-a-word rule to it to show what the cycle time alone is worth. That is an extrapolation and it is the only one here. The manual does not price the 709's synchronizer a word at a time, and nothing on this page claims it does.
The instruction rate falls in proportion to the cycles taken, which is a model
Storage cycles taken is exact: it is a count against a count. Additions lost is a model, and a mild one. An add or subtract is 24 usec on the 709 and 4.8 on the 7090, both exactly two basic cycles, so the page converts stolen cycles to lost additions by dividing by two. Real instruction mixes are not all adds, indirect addressing costs another cycle by the manual's own statement, and a processor waiting on a channel is not the same as a processor short of cycles. The share of core is the claim. The additions are an illustration of it.
No arbitration, no burst mode, no completion interrupt
The multiplexor resolves who reaches core storage and in what order, and none of that is modelled here: this page adds channel demands together and compares the total to what the core can serve. There is no burst versus cycle-steal choice, because the manual describes one word at a time for this machine. The 7090's data channel trap exists and is not modelled. A real transfer also has record gaps, which Chart 2 prices at 7.3 and 10.8 milliseconds and which mean the average rate over a reel is below the character rate this page uses.
The manual's operations-per-second figures are rounded, and it says so
Chart 1 prints 41,660 operations a second for the 709 and 208,330 for the 7090, under the line “Operations-per-second numbers are approximate.” The divisions give 41,666.67 and 208,333.33. The page uses the cycle times, which are exact, and prints the chart's figures only to show they were rounded. Nothing here reproduces a rounded number as though it were the measurement.
The date is the 709 and the manual is the 7090's
The roster dates this to 1958, when the 709 was installed and its data synchronizer appeared. The document read here is the August 1960 General Information Manual for the 7090, which says its data channels replace the data synchronizers and tape control units used with the 709 system.
So the mechanism is the 709's and the numbers are the 7090's, and the page shows both cycle times rather than smoothing that over. This is the same handling Context Switch gives Atlas.
Sources
- IBM, 709/7090 Data Processing System, General Information Manual, August 1960, 16 pages, from the Computer History Museum. Page 4 for the data channel, the 36-bit word and the eight-channel maximum; page 6 for one storage cycle of 2.4 usec a word; Chart 1 for the execution speeds and Chart 2 for the tape rates.
- Logical Art, the studio this belongs to.